1. Field of the Invention
The present invention relates to a field-effect transistor circuit using a metal semiconductor FET (MES FET) formed on a GaAs (gallium arsenide) substrate and, more particularly, to a current-regulating circuit for supplying current to a cascade connection of direct coupled FET logic (DCFL) circuits.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a DCFL inverter circuit as an example of a DCFL circuit. In general, a DCFL circuit can be operated from a low-voltage power supply of 1 to 2 V, and a constant current is carried through the DCFL circuit regardless of the logical state "0" or "1". For example, in the inverter circuit of FIG. 1, a depletion-type load transistor 51, whose gate and drain are connected to each other, and an enhancement-mode driving transistor 52, whose gate receives the input volt age, are connected in series between the source potential V.sub.CC and the ground potential GND. With this inverter circuit, if the source potential V.sub.CC is 1 V, then the output potential will be, for example, 0.05 to 0.1 V when the driving transistor 52 is in an on state, whereas it will be, for example, 0.6 to 0.7 V when the transistor 52 is in an off state.
FIG. 2 is a block diagram of another example of a DCFL circuit. As shown in FIG. 2, for example, a circuit which makes use of the aforementioned feature of DCFL circuits and consists of two DCFL circuits cascade-connected (stacked) in two stages to decrease drawn current has been proposed (Japanese patent application No. 63-116422, filed by the assignee of the present invention). In this circuit, a first (the upper) DCFL circuit 11 and a second (the lower) DCFL circuit 12 are cascade-connected between the source potential V.sub.CC and ground potential GND. The first DCFL circuit 11 is connected across the drain and source of a current-regulating depletion-type MES FET 13. Specifically, the drain of the MES FET 13 is connected to the source potential V.sub.CC and the source thereof is connected to the junction of the upper DCFL circuit 11 and the lower DCFL circuit 12. A bias circuit 14 is connected between the source potential V.sub.CC and ground potential GND. In this case, the bias circuit 14 is a potential divider circuit for bisecting the source potential V.sub.CC, the bisected output of which is applied to the gate of the MES FET 13. When the current flowing through the lower DCFL circuit 12 becomes larger than that flowing through the upper DCFL circuit 11, the MES FET 13 supplies current to the lower DCFL circuit 12 to compensate for the difference in the drawn current between the upper and lower DCFL circuits.
In the circuit of FIG. 2, the lower DCFL circuit 12 is assumed to be a circuit that draws a large amount of current instantaneously like an output circuit. When the lower DCFL circuit 12 has carried a lot of current, the gate-to-source voltage V.sub.GS of the MES FET 13 becomes large so as to supply as much current as required to compensate for the drawn current.
However, since the gate potential of the current-regulating MES FET 13 is fixed to the divided constant output of the potential divider circuit 14, the source potential of the MES FET 13 drops. This makes it impossible to maintain the stable potential at the junction of the upper and lower DCFL circuits 11 and 12, i.e., the stable ground potential (the intermediate ground potential V.sub.GND1) of the upper DCFL circuit 11. This further causes the output potential of the upper DCFL circuit 11 to fluctuate, with the result that a subsequent circuit (not shown) connected to the circuit 11 malfunctions.
In such a conventional current-regulating circuit which supplies compensating current to the cascade-connected DCFL circuits, when a large amount of current are flown through the DCFL circuit to be compensated, the potential at the output terminal of the current-regulating circuit becomes unstable, in order to supply as much current as needed to compensate for the drawn circuit which uses the output terminal of the current-regulating circuit as the intermediate ground potential terminal to fluctuate. This results in the malfunction of a subsequent circuit connected to the DCFL circuit.